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2. on channel turns off while fault exists. 3. low r on. 4. fast switching times. 5. break-before-make switching. switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. trench isolation eliminates latch-up. a dielectric trench separates the p and n-channel mosfets thereby preventing latch-up. ordering guide model temperature range package option * ADG508Fbn ?0 c to +85 c n-16 ADG508Fbrn ?0 c to +85 c r-16n ADG508Fbrw ?0 c to +85 c r-16w adg509fbn ?0 c to +85 c n-16 adg509fbrn ?0 c to +85 c r-16n adg509fbrw ?0 c to +85 c r-16w adg528fbn ?0 c to +85 c n-18 adg528fbp ?0 c to +85 c p-20a * n = plastic dip; p = plastic leaded chip carrier (plcc); rn = 0.15" small outline ic (soic), rw = 0.3" small outline ic (soic). functional block diagrams s1 s8 a0 d ADG508F/adg528f a1 a2 en 1 of 8 decoder adg528f only wr rs s1a a0 da adg509f a1 s4a s1b s4b db en 1 of 4 decoder rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADG508F/adg509f/adg528f * 4/8 channel fault-protected analog multiplexers * patent pending. general description the ADG508F, adg509f, and adg528f are cmos analog multiplexers, the ADG508F and adg528f comprising eight single channels and the adg509f comprising four differential channels. these multiplexers provide fault protection. using a series n-channel, p-channel, n-channel mosfet structure, both device and signal source protection is provided in the event of an overvoltage or power loss. the multiplexer can withstand continuous overvoltage inputs from ?0 v to +55 v. during fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. this protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. the ADG508F and adg528f switch one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1, and a2. the adg509f switches one of four differen- tial inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. the adg528f has on-chip address and control latches that facilitate microprocessor inter- facing. an en input on each device is used to enable or disable the device. when disabled, all channels are switched off. product highlights 1. fault protection. the ADG508F/adg509f/adg528f can withstand con- tinuous voltage inputs from ?0 v to +55 v. when a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows. features low on resistance (300 typ) fast switching times t on 250 ns max t off 250 ns max low power dissipation (3.3 mw max) fault and overvoltage protection (C40 v to +55 v) all switches off with power supply off analog output of on channel clamped within power supplies if an overvoltage occurs latch-up proof construction break before make construction ttl and cmos compatible inputs applications existing multiplexer applications (both fault-protected and nonfault-protected) new designs requiring multiplexer functions one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001
rev. d C2C (v dd = +15 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted) dual supply b version ?0 c to parameter +25 c +85 c unit test conditions/comments analog switch analog signal range v ss + 3 v min v dd ?1.5 v max r on 300 350 ? typ ?0 v < v s < +10 v, i s = 1 ma; v dd = +15 v 10%, v ss = ?5 v 10% 400 ? max ?0 v < v s < +10 v, i s = 1 ma; v dd = +15 v 5%, v ss = ?5 v 5% r on drift 0.6 %/ c typ v s = 0 v, i s = 1 ma r on match 5 % max v s = 0 v, i s = 1 ma leakage currents source off leakage i s (off) 0.02 na typ v d = 10 v, v s = 10 v; 1 50 na max test circuit 2 drain off leakage i d (off) 0.04 na typ v d = 10 v, v s = 10 v; ADG508F/adg528f 1 60 na max test circuit 3 adg509f 1 30 na max channel on leakage i d , i s (on) 0.04 na typ v s = v d = 10 v; ADG508F/adg528f 1 60 na max test circuit 4 adg509f 1 30 na max fault output leakage current 0.02 na typ v s = 33 v, v d = 0 v, test circuit 3 (with overvoltage) 2 2 a max input leakage current 0.005 a typ v s = 25 v, v d = 10 v, test circuit 5 (with overvoltage) 2 a max input leakage current 0.001 a typ v s = 25 v, v d = v en = a0, a1, a2 = 0 v (with power supplies off) 2 a max test circuit 6 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 1 a max v in = 0 or v dd c in , digital input capacitance 5 pf typ dynamic characteristics 1 t transition 200 ns typ r l = 1 m ? , c l = 35 pf; 300 400 ns max v s1 = 10 v, v s8 = 10 v; test circuit 7 t open 50 ns typ r l = 1 k ? , c l = 35 pf; 25 10 ns min v s = 5 v; test circuit 8 t on (en, wr ) 200 ns typ r l = 1 k ? , c l = 35 pf; 250 400 ns max v s = 5 v; test circuit 9 t off (en, rs ) 200 ns typ r l = 1 k ? , c l = 35 pf; 250 400 ns max v s = 5 v; test circuit 9 t sett , settling time 0.1% 1 s typ r l = 1 k ? , c l = 35 pf; 0.01% 2.5 s typ v s = 5 v adg528f only t w , write pulsewidth 100 120 ns min t s , address, enable setup time 100 ns min t h , address, enable hold time 10 ns min t rs , reset pulsewidth 100 ns min charge injection 4 pc typ v s =0v,r s =0 ? ,c l = 1 nf; test circuit 12 off isolation 68 db typ r l = 1 k ? , c l = 15 pf, f = 100 khz; 50 db min v s = 7 v rms; test circuit 13 c s (off) 5 pf typ c d (off) ADG508F/adg528f 50 pf typ adg509f 25 pf typ power requirements i dd 0.1 0.2 ma max v in = 0 v or 5 v i ss 0.1 0.1 ma max notes 1 guaranteed by design, not subject to production test. specifications subject to change without notice. ADG508F/adg509f/adg528f?pecifications
ADG508F/adg509f/adg528f rev. d C3C table i. ADG508F truth table a2 a1 a0 en on switch x x x 0 none 00011 00112 01013 01114 10015 10116 11017 11118 x = don? care table ii. adg509f truth table a1 a0 en on switch pair x x 0 none 0011 0112 1013 1114 x = don? care table iii. adg528f truth table a2 a1 a0 en wr rs on switch x xxx g 1 retains previous switch condition x xxxx0 none (address and enable latches cleared) x x x 0 0 1 none 0 001011 0 011012 0 101013 0 111014 1 001015 1 011016 1 101017 1 111018 x = dont care timing diagrams (adg528f) t w 50% 50% t s t h 0.8v 2v 3v wr 0v 3v 0v a0, a1, a2 en figure 1. figure 1 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; there- fore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . t rs 50% 50% 0.8v o 3v rs 0v v o switch output t off ( rs ) 0v figure 2. figure 2 shows the reset pulsewidth, t rs , and the reset turn- off time, t off ( rs ). note: all digital input signals rise and fall times are measured from 10% to 90% of 3 v. t r = t f = 20 ns.
rev. d C4C ADG508F/adg509f/adg528f absolute maximum ratings * (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?5 v v en , v a digital input . . . . . . . 0.3 v to v dd + 2 v or 20 ma, whichever occurs first v s , analog input overvoltage with power on . . . . . v ss ?25 v to v dd + 40 v v s , analog input overvoltage with power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0 v to +55 v continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) . . . . . . . . . . . 40 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c plastic package ja , thermal impedance 16-lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 c 18-lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 c lead temperature, soldering (10 sec) . . . . . . . . . . . . 260 c soic package ja , thermal impedance narrow body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 c/w wide body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c plcc package ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 90 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. ADG508F/adg509f pin configurations dip/soic dip/soic a0 en a1 a2 s2 s3 s4 s5 s6 s7 s1 gnd v dd ds8 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ADG508F v ss a0 en a1 gnd s2a s3a s4a s2b s3b s4b v ss s1a v dd s1b da db 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) adg509f adg528f pin configurations dip plcc wr a0 rs a1 s1 s2 s3 s5 s6 en v ss a2 s4 s7 d s8 v dd gnd 1 2 18 17 5 6 7 14 13 12 3 4 16 15 811 910 top view (not to scale) adg528f en v ss s3 s1 s2 a0 wr a1 nc rs 19 31 220 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) adg528f a2 gnd s6 v dd s5 s4 d s7 s8 nc nc = no connect caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADG508F/adg509f/adg528f features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ADG508F/adg509f/adg528f rev. d C5C terminology v dd most positive power supply potential. v ss most negative power supply potential. gnd ground (0 v) reference. r on ohmic resistance between d and s. r on drift change in r on when temperature changes by one degree celsius. r on match dif ference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the s witch is on. v d (v s ) analog voltage on terminals d, s. c s (off) c hannel i nput capacitance for off?condi tion. c d (off) channel output capacitance for ?ff?condi tion. c d , c s (on) ?n?switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch ?n?condition. t off (en) delay time between the 50% and 90% points of the digital input and switch ?ff?condi tion. t transition delay time between the 50% and 90% points of the digital inputs and the switch ?n condition when switching from one address state to another. t open off?time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic ?? v inh minimum input voltage for logic ?? i inl (i inh ) input current of the digital input. off isolation a measure of unwanted signal coupling through an ?ff?channel. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current. typical performance characteristics 2000 1000 0 ?5 ? 15 5 010 ?0 500 1750 1500 1250 750 250 v d (v s ) ?v r on ? t a = 25 c v dd = +5v v ss = ?v v dd = +10v v ss = ?0v v dd = +15v v ss = ?5v tpc 1. on resistance as a function of v d (v s ) 1m 1 1p 50 30 50 10 20 20 40 1n 30 40 100 10 10n 100n 10p 100p 10 0 v in input voltage v i s input leakage a v dd = 0v v ss = 0v v d = 0v 60 operating range tpc 2. input leakage current as a function of v s (power supplies off) during overvoltage conditions 1m 1 1p 50 30 50 10 20 20 40 1n 30 40 100 10 10n 100n 10p 100p 10 0 v in input voltage v i d input leakage a v dd = +15v v ss = 15v v d = 0v 60 operating range )*+$ , 0 1 + %

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rev. d C6C ADG508F/adg509f/adg528f 2000 1000 0 15 515 5 010 10 500 1750 1500 1250 750 250 v d ( v s ) v r on 25 c v dd = +15v v ss = 15v 125 c 85 c tpc 4. on resistance as a function of v d (v s ) for different temperatures 1m 1 1p 50 30 50 10 20 20 40 1n 30 40 100 10 10n 100n 10p 100p 10 0 v in input voltage v i s input leakage a v dd = +15v v ss = 15v v d = 0v 60 operating range tpc 5. input leakage current as a function of v s (power supplies on) during overvoltage conditions 0.3 0.2 0.2 14 614 2 26 10 0.1 10 0.0 0.1 v s , v d v leakage currents na i s (off) i d (off) i d (on) v dd = +15v v ss = 15v t a = 25 c tpc 6. leakage currents as a function of v d (v s ) 100 10 0.01 25 45 125 65 55 75 35 1 115 0.1 temperature c leakage currents na i s (off) i d (off) i d (on) v dd = +15v v ss = 15v v d = +10v v s = 10v 85 95 105 tpc 7. leakage currents as a function of temperature 260 240 100 10 15 12 13 11 120 14 t on (en) v in = 2v 220 200 180 160 140 t ns v supply v t off (en) t transition tpc 8. switching time vs. power supply 280 240 100 25 125 65 85 45 120 105 t on (en) 220 200 180 160 140 t ns temperature c t off (en) t transition 260 v dd = +15v v ss = 15v v in = +5v tpc 9. switching time vs. temperature
ADG508F/adg509f/adg528f rev. d C7C theory of operation the ADG508F/adg509f/adg528f multiplexers are capable of withstanding overvoltages from ?0 v to +55 v, irrespective of whether the power supplies are present or not. each channel of the multiplexer consists of an n-channel mosfet, a p-channel mosfet, and an n-channel mosfet, connected in series. when the analog input exceeds the power supplies, one of the mosfets will switch off, limiting the current to submicroamp levels, thereby preventing the overvoltage from damaging any circu itry following the multiplexer. figure 3 illustrates the channel architecture that enables these multiplexers to withstand continuous overvoltages. when an analog input of v ss + 3 v to v dd ?1.5 v is applied to the ADG508F/adg509f/adg528f, the multiplexer behaves as a standard multiplexer, with specifications similar to a stan- dard multiplexer, for example, the on-resistance is 400 ? maximum. however, when an overvoltage is applied to the device, one of the three mosfets will turn off. figures 3 to 6 show the conditions of the three mosfets for the various overvoltage situations. when the analog input ap plied to an on channel approaches the positive power supply line, the n-channel mosfet turns off since the voltage on the analog input exceeds the difference between v dd and the n-channel q1 q2 q3 +55v overvoltage n-channel mosfet is off v dd v ss figure 3. +55 v overvoltage input to the on channel q1 q2 q3 40v overvoltage n-channel mosfet is on v dd v ss p-channel mosfet is off figure 4. C40 v overvoltage on an off channel with multiplexer power on threshold voltage (v tn ). when a voltage more negative than v ss is applied to the multiplexer, the p-channel mosfet will turn off since the analog input is more negative than the difference between v ss and the p-channel threshold voltage (v tp ). since v tn is nominally 1.5 v and v tp is typically 3 v, the analog input range to the multiplexer is limited to ?2 v to +13.5 v when a 15 v power supply is used. when the power supplies are present but the channel is off, again either the p-channel mosfet or one of the n-channel mosfets will turn off when an overvoltage occurs. finally, when the power supplies are off, the gate of each mosfet will be at ground. a negative overvoltage switches on the first n-channel mosfet but the bias produced by the overvoltage causes the p-channel mosfet to remain turned off. with a positive overvoltage, the first mosfet in the series will remain off since the gate to source voltage applied to this mosfet is negative. during fault conditions, the leakage current into and out of the ADG508F/adg509f/adg528f is limited to a few microamps. this protects the multiplexer and succeeding circuitry from over stresses as well as protecting the signal sources which drive the multiplexer. also, the other channels of the multi- plexer will be undisturbed by the overvoltage and will continue to operate normally. q1 q2 q3 +55v overvoltage n-channel mosfet is off figure 5. +55 v overvoltage with power off q1 q2 q3 40v overvoltage n-channel mosfet is on p-channel mosfet is off figure 6. C40 v overvoltage with power off
rev. d C8C ADG508F/adg509f/adg528f test circuits i ds s r on = v 1 /i ds v1 v s d test circuit 1. on resistance v s i s (off) v d s1 s2 s8 v ss v dd v ss v dd 0.8v d en a test circuit 2. i s (off) v d s1 s2 s8 v s v ss v dd i d (off) v ss v dd 0.8v d en a test circuit 3. i d (off) i d (on) v d s1 s8 v s v ss v dd v ss v dd 2.4v d en a s2 test circuit 4. i d (on) v d s1 s2 s8 v s v ss v dd v ss v dd 0.8v d en a test circuit 5. input leakage current (with overvoltage) a2 v s 0v 0v v ss v dd d 0v a * similar connection for ADG508F/adg509f a1 a0 en rs gnd wr adg528f * s1 s8 test circuit 6. input leakage current (with power supplies off) 3v 50% v out t transition 90% 90% t transition address drive (v in ) 50% a2 v out v ss v dd d v s1 * similar connection for ADG508F/adg509f a1 a0 en rs gnd wr adg528f * s1 s8 s2 s7 v in 2.4v 50 v s8 r l 1m c l 35pf v ss v dd test circuit 7. switching time of multiplexer, t transition
ADG508F/adg509f/adg528f rev. d C9C a2 v out v ss v dd d v s * similar connection for ADG508F/adg509f a1 a0 en rs gnd wr adg528f * s1 s8 s2 s7 v in 2.4v 50 r l 1k c l 35pf v ss v dd address drive (v in ) 3v v out t open 80% 80% test circuit 8. break-before-make delay, t open 2.4v 3v 50% output 0.9v o 50% t on (en) 0.9v o 0v v o 0v t off (en) enable drive (v in ) a2 v out v ss v dd d v s * similar connection for ADG508F/adg509f a1 a0 rs gnd wr adg528f * s1 s2 s8 v in 50 r l 1k c l 35pf v ss v dd en test circuit 9. enable delay, t on (en), t off (en) 3v output wr 0.2v o 50% t on ( wr ) 0v v o 0v a2 v out v ss v dd d v s a1 a0 en rs gnd adg528f s1 s2 s8 2.4v r l 1k c l 35pf v ss v dd wr v wr v rs test circuit 10. write turn-on time, t on ( wr )
rev. d C10C ADG508F/adg509f/adg528f 3v 50% rs switch output 0.8v o 50% t rs t off ( rs ) 0v 0v v o a2 v out v ss v dd d v s a1 a0 en rs gnd wr adg528f s1 s2 s8 v in 2.4v r l 1k c l 35pf v ss v dd test circuit 11. reset turn-off time, t off ( rs ) v out 3v v out logic input (v in ) q inj = c l x v out 0v a2 v out v ss v dd d * similar connection for ADG508F/adg509f a1 a0 en rs gnd wr adg528f * v in 2.4v c l 1nf v ss v dd s r s v s test circuit 12. charge injection a2 v out v ss v dd d * similar connection for ADG508F/adg509f a1 a0 en rs gnd wr adg528f * 2.4v r l 1k v ss v dd s1 v in s8 test circuit 13. off isolation
ADG508F/adg509f/adg528f rev. d C11C 16-lead plastic (n-16) 16 18 9 pin 1 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) outline dimensions dimensions shown in inches and (mm). 16-lead soic (r-16w) (wide body) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.050 (1.27) bsc 16 9 8 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 0.4133 (10.50) 0.3977 (10.00) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) 16-lead soic (r-16n) (narrow body) 16 9 8 1 0.1574 (4.00) 0.1497 (3.80) 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) bsc pin 1 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19)
rev. d C12C ADG508F/adg509f/adg528f outline dimensions dimensions shown in inches and (mm). c00035cC0C4/01(d) printed in u.s.a. 18-lead plastic (n-18) 18 19 10 0.925 (23.49) 0.845 (21.47) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead plcc (p-20a) 3 pin 1 identifier 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.02) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) ADG508F/adg509f/adg528f revision history location page data sheet changed from rev. c to rev. d. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 max ratings changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted 16-lead cerdip from outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 deleted 18-lead cerdip from outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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